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16 - bit, 200 msps/250 msps analog - to - digital converter data sh eet ad9467 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no resp onsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 75.5 dbfs snr to 21 0 mhz at 250 msps 90 dbfs sfdr to 30 0 mhz at 250 msps sfdr at 170 mhz at 2 50 msps 92 dbfs at ?1 dbfs 100 dbfs at ?2 dbfs 60 fs rms j itter excellent linearity at 250 msps dnl = 0.5 lsb typical inl = 3.5 lsb typical 2 v p - p to 2.5 v p -p (default) differential full - scale input (programmable) integrated i nput b uffer external r eference s upport o ption clock duty cycle stabilizer output clock available serial port control built - in selectable digital test pattern generation selectable o utput d ata f ormat lvds o utputs (ansi - 644 compatible) 1.8 v and 3.3 v supply operation applications multicarrier, multimode cellular receivers antenna array positioning power amplifier linearization broadband wireless radar infrared i maging communica tions instrumentation general description the ad9467 is a 16 - bit, monolithic, if sampling analog - to - digital converter (adc). it is optimized for high performance over wide bandwidths and ease of use. the product operates at a 250 msps conversion rate and is designed for wireless re ceivers , instrumentation , and test equipment that require a high dynamic range . the adc requires 1.8 v and 3.3 v power supplies and a low voltage differe n tial input clock for full performance operation. no e x ternal reference or d river components are required for many applications. data outputs are lvds compatible (ansi - 644 compatible) and include the means to reduce the overall cu r rent needed for short trace distances. functional block dia gram 16 2 16 2 pipeline adc clock and timing management ref l vds output st aging a vdd1 (1.8v) dr vdd (1.8v) a vdd2 (3.3v) a vdd3 (1.8v) spivdd (1.8v t o 3.3v) xvref agnd drgnd ad9467 buffer vin+ clk+ clk? vin? csb sdio sclk or+/or? d15+/d15? to d0+/d0? dco+/dco? 09029-001 figure 1. a data clock output (dco) for capturing data on the output is provided for signaling a new output bit . the i nternal p ower - down feature supported vi a the spi typically consumes less than 5 mw when disabled. optional features allow users to implement various selectable operating cond i tions, including input range, data format select, and output data test patterns. the ad9467 is available in a pb - free, 72 - lead, lfcsp specified over the ? 40c to +85c industrial te m perature range . product highlights 1. if optimization capability used to improve sfdr . 2. outstanding sfdr performance for if sampling applications such as multicarrier, multimode 3g, and 4g cellular base station receivers. 3. ease of use: on - chip reference , high input impedance buffer , adjustable ana log input range , and an output clock to simplify data capture. 4. packaged in a pb - free, 72 - lead lfcsp package. 5. clock duty cycle stabilizer (dcs) maintains overall adc performance over a wide range of input clock pulse widths. 6. standard serial port interface (spi) supports various product features and functions, such as data formatting (offset b i nary, twos complement, or gray coding ).
ad9467 data sheet rev. d | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 6 switching specifications .............................................................. 7 absolute maximum ratings ............................................................ 8 thermal impedance ..................................................................... 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 equivalent circuits ......................................................................... 11 typical performance characteristic s ........................................... 12 theory of operation ...................................................................... 19 analog input considerations ................................................... 19 clock input considerations ...................................................... 22 serial port interface (spi) .............................................................. 26 hardware interface ..................................................................... 26 memory map .................................................................................. 28 reading the memory map table .............................................. 28 reserved locations .................................................................... 28 default values ............................................................................. 28 logic levels ................................................................................. 28 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 2 /1 3 rev. c to rev. d changes to figure 1 .......................................................................... 1 changes to figure 2 .......................................................................... 7 changes to vin+, vin? parameter rating, table 5 ................... 8 changes to figure 51, figure 52, and figure 53 ......................... 20 changes to figure 54 and figure 56 ............................................. 21 changes to digital outputs and timing section ....................... 24 deleted addr. (hex) 17 row, table 13 ......................................... 29 updated outline dimensions ....................................................... 32 changes to ordering guide .......................................................... 32 9/11 rev. b to rev. c changes to figure 4 4 a nd figure 45 ............................................. 17 3/11 rev. a to rev. b change parameter name to full power bandwidth, table 1 ...... 3 changes to switching specifications, table 4 ............................... 7 change to vin+, vin? parameter, table 5 .................................. 8 deleted figure 43 ............................................................................ 17 added new figure 43 ..................................................................... 17 2 /11 rev. 0 to rev. a changes to features section ............................................................ 1 added figure 24 and figure 25; renumbered sequentially ..... 14 changes to differential configurations section and figure 54 .......................................................................................... 21 added figure 55 to figure 5 7 ....................................................... 21 changes to figure 65 and figure 66 ............................................ 24 changes to addr. (hex) 15, bits[2:0], addr. (hex) 10, bits[7:0], and addr. (hex) 10, default notes column ............................... 29 changes to addr. (hex) 36, default value (hex) column and addr. (hex) 1 07, default value (hex) column ......................... 30 10/ 10 revision 0: initial version
data sheet ad9467 rev. d | page 3 of 32 specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, spec ified maximum sampling rate, 2 .5 v p - p differential input, 1.25 v internal reference , ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 1. ad9467bcpz - 200 ad9467bcpz - 250 parameter 1 temp min typ max min typ max unit resolution 16 16 bits accuracy no missing codes full g uaranteed guaranteed offset error full ? 150 0 + 150 ? 150 0 + 150 lsb gain error full ? 3.5 ? 0.2 + 2.5 ? 3.5 ? 0.1 + 2.5 %fsr differential nonlinearity (dnl) 2 full ? 0.8 0.4 + 0.7 ? 0.6 0.5 + 1.3 lsb integral nonlinearity (inl) 2 full ? 9.5 5 + 9.5 ? 11.8 3 .5 + 9.5 lsb temperature drift offset error full 0.020 0.023 %fs r/ c gain error full 0.011 0.036 %fs r/ c analog inputs differential input voltage range (internal vref = 1 v to 1.25 v) full 2 2.5 2.5 2 2.5 2.5 v p - p common - mode voltage 25c 2. 3 2.1 5 v differential input resistance 25c 530 530 ? differential input capacitance 25c 3.5 3.5 pf full power bandwidth 25c 900 900 mhz xvref input input voltage ful l 1 1.25 1 1.25 v input capacitance full 3 3 pf power supply avdd1 full 1.75 1.8 1.85 1.75 1.8 1.85 v avdd2 full 3.0 3.3 3.6 3.0 3.3 3.6 v avdd3 full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd1 full 485 536 58 0 514 567 618 ma i avdd2 full 49 55 61 49 55 61 ma i avdd3 full 21 24 27 27 31 35 ma i drvdd full 35 38 41 36 40 43 ma total power dissipation (including output drivers) full 1.14 1.26 1.37 1.2 1.33 1.45 w power - down dissipation full 4.4 90 4.4 90 mw 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 measured with a low input frequency, full - scale sine wave, with approximately 5 pf loading on each output bit.
ad9467 data sheet rev. d | page 4 of 32 ac specifications avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, spec ified maximum sampling rate , 2.5 v p - p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 2. ad9467bcpz - 200 ad9467bcpz - 250 parameter 1 temp min typ max min typ max unit analog input full scale 2.5 2/2.5 2.5 2/2.5 v p-p signal- to - noise ratio (snr) f in = 5 mhz 25c 74.6/76. 4 74.7/76.4 dbfs f in = 97 mhz 25c 75.1 74.5/76. 2 74.5/76.1 dbfs f in = 97 mhz full 73.8 dbfs f in = 140 mhz 25c 74.3/76.0 74.4/76.0 dbfs f in = 170 mhz 25c 74.2/75.8 74.7 74.3/75.8 dbfs f in = 170 mhz full 72.3 dbfs f in = 210 mhz 25c 73.9/75.5 74.0/75.5 dbfs f in = 300 mhz 25c 73.5/74.7 73.3/74.6 dbfs signal- to - noise and distortion ratio (sinad) f in = 5 mhz 25c 74.6/76.3 74.6/76.3 dbfs f in = 97 mhz 25c 74 .7 74.5/76.2 74.4/76.0 dbfs f in = 97 mhz full 73 .1 dbfs f in = 140 mhz 25c 74.3/75.9 74.4/76.0 dbfs f in = 170 mhz 25c 74.1/75.6 74 .4 74.2/75.8 dbfs f in = 170 mhz full 71 .8 dbfs f in = 210 mhz 25c 73.9/75.3 73.9/75.4 dbfs f in = 300 mhz 25c 73.3/74.3 73.1/74.4 dbfs effective number of bits (enob) f in = 5 mhz 25c 12.1/12.4 12.1/12.4 bits f in = 97 mhz 25c 12.1/12.4 12.1/12.3 bits f in = 97 mhz full bits f in = 140 mhz 25c 12.1/12.3 12.1/12.3 bits f in = 170 mhz 25c 12.0/12.3 12.0/12.3 bits f in = 170 mhz full bits f in = 210 mhz 25c 12.0/12.2 12.0/12.2 bits f in = 300 mhz 25c 11.9/12.0 11.9/12.1 bits spurious - free dynamic range (sfdr) (including second and third harmonic distortion ) 2 f in = 5 mhz 25c 95/95 98/97 dbfs f in = 97 mhz 25c 86 95/95 95/93 dbfs f in = 97 mhz full 83 dbfs f in = 140 mhz 25c 94/93 94/95 dbfs f in = 170 mhz 25c 95/90 84 93/92 dbfs f in = 170 mhz full 8 4 dbfs f in = 210 mhz 25c 93/88 93/92 dbfs f in = 300 mhz 25c 92 /8 6 93/90 dbfs spurious - free dynamic range (sfdr) ( including second and third harmonic distortion ) 2 f in = 5 mhz @ ? 2 db full scale full 100/96 100/100 dbfs f in = 97 mhz @ ? 2 db full scale full 100/98 97/97 dbfs f in = 140 mhz @ ? 2 db full scale full 98/96 100/95 dbfs f in = 170 mhz @ ? 2 db full scale full 96/93 100/100 dbfs f in = 210 mhz @ ? 2 db full scale full 94/93 93/93 dbfs f in = 300 mhz @ ? 2 db full scale full 90/89 90/90 dbfs
data sheet ad9467 rev. d | page 5 of 32 ad9467bcpz - 200 ad9467bcpz - 250 parameter 1 temp min typ max min typ max unit worst other (excluding second and third harmonic distortion) 2 f in = 5 mhz 25c 96/98 98/97 dbfs f in = 97 mhz 25c 86 97/97 97/93 dbfs f in = 97 mhz full 83 dbfs f in = 140 mhz 25c 97/96 97/95 dbfs f in = 170 mhz 25c 98/98 90 97/93 dbfs f in = 170 mhz full 87 dbfs f in = 210 mhz 25c 96/97 97/95 dbfs f in = 300 mhz 25c 95/95 97/95 dbfs two - tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs @ 2.5 v p- p fs f in1 = 70 mhz, f in2 = 72 mhz 25c 95 97 dbfs f in1 = 170 mhz, f in2 = 172 mhz 25c 93 91 dbfs 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 see the sfdr optimization buffer current adjustment section for optimum settings.
ad9467 data sheet rev. d | page 6 of 32 digital specificatio ns av d d1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, specified maximum s ampling rate, 2 .5 v p - p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 3. ad9467bcpz - 200 ad9467bcpz - 250 parameter 1 temp min typ max min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl differential input voltage 2 full 250 250 mv p -p input common - mode voltage full 0.8 0.8 v input resistance (differential) 25c 20 20 k? input capacitance 25c 2.5 2.5 pf logic inputs (sclk, csb, sdio) logic 1 voltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0.3 0.3 v input resistance 25c 30 30 k ? input capacitance 25c 0.5 0.5 pf logic output (sdio) 3 logic 1 vol tage (i oh = 800 a) full 1.7/3.1 1.7/3.1 v logic 0 voltage (i ol = 50 a) full 0.3 0.3 v digital outputs (d0+ to d15+, d0? to d15?, dco+, dco? , or +, or? ) logic compliance lvds lvds differential output voltage (v od ) full 247 545 2 47 545 mv output offset voltage (v os ) full 1.125 1.375 1.125 1.375 v output coding (default) offset binary offset binary 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 this is specified for lvds and lvpecl only. 3 this depends on if spivdd is tied to a 1.8 v or 3.3 v supply.
data sheet ad9467 rev. d | page 7 of 32 switching specificat ions avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, drvdd = 1.8 v, spec ified maximum sampling rate, 2 .5 v p - p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted. table 4. ad9467bcpz - 200 ad9467bcpz - 250 parameter 1 temp min typ max min typ max unit clock 2 clock rate full 50 2 00 50 250 msps clock pulse width high (t ch ) full 2.5 2 ns clock pulse width low (t cl ) full 2.5 2 ns output parameters 2 , 3 propagation delay (t pd ) 25c 3 3 ns rise time (t r ) (20% to 80%) 25 c 200 200 ps fall time (t f ) (20% to 80%) 25c 200 200 ps dco propagation delay (t cpd ) 25c 3 3 ns dco to data delay (t skew ) full ? 20 0 +2 00 ? 20 0 +2 00 ps wake - up time (power - down) full 100 100 ms pipeline latency full 16 16 clock cycles aperture aperture delay (t a ) 25c 1.2 1.2 ns aperture uncertainty (jitter) 25c 60 60 fs rms out - of - range recovery ti me 25c 1 1 clock cycles 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 can be adjusted via the spi interface. 3 measurements were made using a part soldered to fr - 4 material. timing diagrams 09029-002 n ? 1 n + 1 n + 2 n + 3 n + 4 n + 5 n t a t ch t cl 1/fs t skew t cpd t pd clk+ clk? dco+ dco? d15+/d14+ (msb) d15?/d14? (msb) d1+/d0+ (lsb) d1?/d0? (lsb) vin d15 d14 n ? 16 n ? 16 n ? 15 n ? 15 n ? 14 n ? 13 n ? 12 n ? 11 n ? 10 n ? 10 n ? 16 n ? 16 n ? 15 n ? 15 n ? 14 n ? 13 n ? 12 n ? 11 n ? 10 n ? 10 d1 d0 . . . figure 2 . 16 - bit output data timing
ad9467 data sheet rev. d | page 8 of 32 absolute maximum rat ings table 5. parameter with respect to rating electrical avdd 1 , avdd3 agnd ? 0.3 v to +2.0 v avdd2 , spi vdd agnd ?0.3 v to +3.9 v drvdd dr gnd ?0.3 v to +2.0 v agnd drgnd ?0.3 v to +0.3 v avdd2 , spi vdd avdd1 , avdd3 ?2.0 v to +3.9 v avdd 1 , avdd3 drvdd ?2.0 v to +2.0 v avdd2 , spi vdd drvdd ?2.0 v to +3.9 v digital outputs (dx+, dx ? , or+, or ?, d co+, dco ?) drgnd ?0.3 v to drvdd + 0.2 v clk+, clk? agnd ?0.3 v to avdd1 + 0.2 v vin+, vin ? agnd ?0.3 v to + 3.6 v xvref agnd ?0.3 v to avdd1 + 0.2 v sclk, csb , sdio agnd ?0.3 v to spivdd + 0.2 v environmental operating temperature range (ambient) ?40 c to +85 c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the devi ce. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impedance table 6. air flow velocity (m/s ec ) ja 1, 2 jb 1, 3, 4 jc 1, 5 unit 0.0 15.7c/w 7.5c/w 0.5 c/w 1.0 13.7c/w n/a n/a c/w 2.5 12.3c/w n/a n/a c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per jedec jesd51 -8 (still air). 4 n/a = not applicable. 5 per mil - std 883, method 1012.1. esd caution
data sheet ad9467 rev. d | page 9 of 32 pin configuration and function descripti ons 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd1 avdd1 avdd1 avdd1 clk+ clk? avdd1 avdd1 avdd1 agnd avdd1 avdd1 avdd1 agnd avdd1 agnd 17 drgnd 18 drvdd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 d1?/d0? d1+/d0+ d3?/d2? d3+/d2+ d5?/d4? d5+/d4+ d7?/d6? d7+/d6+ dco? dco+ d9?/d8? d9+/d8+ d11?/d10? d11+/d10+ d13?/d12? d13+/d12+ 35 d15?/d14? 36 d15+/d14+ 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 avdd1 avdd1 avdd1 spivdd csb sclk sdio dnc avdd1 agnd avdd3 agnd avdd3 agnd or+ or? drgnd drvdd notes 1. dnc = do not connect. 2. exposed thermal pad must be connected to agnd. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd1 avdd1 avdd1 avdd2 avdd2 vin? vin+ avdd2 avdd2 avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 xvref avdd1 avdd1 09029-003 pin 1 indic at or ad9467 top view (not to scale) figure 3. pin configuration , top view table 7 . pin function descrip tions pin no. mnemonic description 0 epad exposed paddle. the exposed paddle must be connected to agnd. 10, 14, 16, 41, 43, 45 agnd analog ground . 1, 2, 3, 4, 7, 8, 9, 11, 12, 13, 15 , 46 , 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 70, 71, 72 avdd 1 1.8 v analog supply . 64, 65, 68, 69 avdd2 3.3 v analog supply . 42, 44 avdd3 1.8 v analog supply. 51 spi vdd 1.8 v or 3.3 v spi supply 17, 38 drgnd digital output driver ground . 18, 37 drvdd 1.8 v digital output driver supply . 67 vin ? analog input complem ent . 66 vin + analog input true . 6 clk? clock input complement . 5 clk+ clock input true . 19 d1?/ d0? d1 and d0 (lsb) digital output c omplement . 20 d1+/ d0+ d1 and d0 (lsb) digital output true . 21 d3?/ d2? d3 and d2 digital output complement . 22 d3+/ d2+ d3 and d2 digital output true . 23 d5?/ d4? d5 and d4 digital output complement . 24 d5+/ d4+ d5 and d 4 digital output true . 25 d7?/ d6? d7 and d 6 digital output complement . 26 d7+/ d6+ d7 and d 6 digital output true . 29 d9?/ d8 ? d9 and d8 digital output c omplement . 30 d9+/ d8 + d9 and d8 digital output true . 31 d11?/d10 ? d11 and d10 digital output complement . 32 d11+/d10 + d11 and d10 digital output true . 33 d13?/d12 ? d13 and d12 digital output complement . 34 d13+/d12 + d13 and d12 digital output true . 35 d15?/d14 ? d15 (msb) and d14 digital output complement .
ad9467 data sheet rev. d | page 10 of 32 pin no. mnemonic description 36 d15+/d14 + d15 (msb) and d14 digital output true . 27 dco ? data clock digital output complement . 28 dco+ data clock digital output true . 39 or ? out - of - range digital output complement . 40 or+ out - of - range digital output true . 47 dnc do not connect ( leave pin floating ). 48 sdio serial data input / output . 49 sclk serial clock . 50 csb chip select bar . 57 xvref external vref option.
data sheet ad9467 rev. d | page 11 of 32 equivalent circuits vin+ avdd2 buf vin? avdd2 buf 265? 265? buf avdd2 v cml 2.15v/2.30v 09029-004 figure 4. e quivalent analog input circuit 0.8v 10k? 10k? 10k? 10k? clk+ clk? avdd1 09029-005 figure 5 . equivalent clock input circuit dr vdd drgnd dx? dx+ v v v v 09029-007 figure 6 . equivalent digital output circuit sclk, sdio and csb 30k? 345? 09029-008 figure 7 . equivalent sclk , sdio , and csb input circ uit 09029-011 spivdd sdio figure 8 . equivalent sdio output circuit 09029-109 1k? 3pf xvref figure 9 . equivalent external vref input circuit ( when enabled )
ad9467 data sheet rev. d | page 12 of 32 typical performance characteristics avdd1 = 1.8 v, avdd2 = 3.3 v, avdd3 = 1.8 v, dr vdd = 1.8 v, specified maximum sampling rate, 2.5 v p - p differential input, 1.25 v internal reference, ain = ?1.0 dbfs, dcs on, default spi settings, unless otherwise noted, b uffer c urrent o ptimized for best sfdr performance. 0 10 20 30 40 60 70 90 50 80 100 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-110 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 76.5dbfs enob = 12.4 bits sfdr = 95.4dbfs figure 10 . single -tone fft with f in = 4.3 mhz, 2.5 v p - p fs , ad9467 - 200 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 60 70 90 50 80 100 09029-111 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 76.2dbfs enob = 12.3 bits sfdr = 92.0dbfs figure 11 . single - tone fft with f in = 97.3 mhz, 2.5 v p - p fs, ad9467 - 200 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 60 70 90 50 80 100 09029-112 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.9dbfs enob = 12.3 bits sfdr = 95.2dbfs figure 12 . single -tone fft with f in = 140 .3 mhz, 2.5 v p - p fs , ad9467 - 200 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 10 20 30 40 60 70 90 50 80 100 09029-113 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.8dbfs enob = 12.3 bits sfdr = 94.1dbfs figure 13 . single -tone fft with f in = 170 .3 mhz, 2.5 v p - p fs , ad9467 - 200 0 10 20 30 40 60 70 90 50 80 100 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-114 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.5dbfs enob = 12.1 bits sfdr = 90.0dbfs figure 14 . single -tone fft with f in = 21 0.3 mhz, 2.5 v p - p fs , ad9467 - 200 0 10 20 30 40 60 70 90 50 80 100 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-115 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 74.7dbfs enob = 12.0 bits sfdr = 86.5dbfs figure 15 . single -tone fft with f in = 29 0.3 mhz, 2.5 v p - p fs, ad9467 - 200
data sheet ad9467 rev. d | page 13 of 32 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-116 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 76.4dbfs enob = 12.4 bits sfdr = 100.0dbfs figure 16 . single -tone fft with f in = 4.3 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-117 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.9dbfs enob = 12.3 bits sfdr = 94.8dbfs figure 17 . single -tone fft with f in = 97 .3 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-118 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 76.0dbfs enob = 12.2 bits sfdr = 93.6dbfs figure 18 . single -tone fft wi th f in = 140.3 mhz, 2.5 v p - p fs, ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-119 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.8dbfs enob = 12.2 bits sfdr = 94.1dbfs figure 19 . sin gle -tone fft with f in = 170 .3 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-120 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 75.5dbfs enob = 12.1 bits sfdr = 90.8dbfs figure 20 . single -tone fft with f in = 21 0.3 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 09029-121 amplitude (dbfs) frequency (mhz) ain = ?1.0dbfs snr = 74.2dbfs enob = 12.0 bits sfdr = 91.0dbfs figure 21 . single -tone fft with f in = 300 .3 mhz, 2.5 v p - p fs, ad9467 - 250
ad9467 data sheet rev. d | page 14 of 32 70 75 80 85 90 95 100 105 1 10 71 72 73 74 75 76 77 78 100 120 140 160 180 200 220 sfdr (dbfs) snr (dbfs) sample r a te (msps) sfdr snr 09029-123 figure 22 . snr/sfdr vs. f sample , f in = 97.3 mhz, 2.5 v p - p fs, ad9467 - 200 210 215 220 225 230 235 240 245 250 70 75 80 85 90 95 100 105 1 10 71 72 73 74 75 76 77 78 sfdr (dbfs) snr (dbfs) sample r a te (msps) sfdr snr 09029-125 figure 23 . snr/sfdr vs . f sample , f in = 97.3 mhz, 2.5 v p - p fs, ad9467 - 250 80 85 90 95 100 105 100 120 140 160 180 200 220 sfdr (dbfs) sample r a te (msps) f in = 4.3mhz f in = 97.3mhz f in = 170.3mhz f in = 290.3mhz 09029-224 figure 24 . sfdr vs. f sample , 2.5 v p - p fs, ad9467 - 200 80 82 84 86 88 90 92 94 96 98 100 160 170 180 190 200 210 220 230 240 250 sfdr (dbfs) sample r a te (msps) 09029-225 f in = 4.3mhz f in = 97.3mhz f in = 170.3mhz f in = 300.3mhz figure 25 . sfdr vs. f sample , 2.5 v p - p fs, ad9467 - 250 70 75 80 85 90 95 100 105 1 10 71 72 73 74 75 76 77 78 0 50 100 150 200 250 300 sfdr (dbfs) snr (dbfs) analog input frequenc y (mhz) snr = 2.0v p-p fs snr = 2.5v p-p fs sfdr = 2.0v p-p fs sfdr = 2.5v p-p fs 09029-126 figure 26 . snr/sfdr vs. f in , 2.0/2.5 v p - p fs, ad9467 - 200 70 75 80 85 90 95 100 105 1 10 71 72 73 74 75 76 77 78 0 50 100 150 200 250 300 sfdr (dbfs) snr (dbfs) analog input frequenc y (mhz) snr = 2.0v p-p fs snr = 2.5v p-p fs sfdr = 2.0v p-p fs sfdr = 2.5v p-p fs 09029-127 figure 27 . snr/sfdr vs. f in , 2.0/2.5 v p - p fs, ad9467 - 250
data sheet ad9467 rev. d | page 15 of 32 0 10 20 30 40 60 70 90 50 80 100 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 94.6dbfs imd2 = 94.6dbfs imd3 = 95.9dbfs 09029-128 figure 28 . two -tone fft with f in1 = 70 mhz and f in2 = 72 mhz, 2.5 v p - p fs , ad9467 - 200 0 10 20 30 40 60 70 90 50 80 100 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 92.7dbfs imd2 = 98.2dbfs imd3 = 92.7dbfs 09029-129 figure 29 . two - tone fft with f in1 = 170 mhz and f in2 = 172 mhz, 2.5 v p - p fs , ad9467 - 200 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 96.7dbfs imd2 = 103.2dbfs imd3 = 96.7dbfs 09029-130 figure 30 . two -tone fft with f in1 = 70 mhz and f in2 = 72 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 100 80 120 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 91.3dbfs imd2 = 96.3dbfs imd3 = 91.3dbfs 09029-131 figure 31 . two -tone fft with f in1 = 170 mhz and f in2 = 172 mhz, 2.5 v p - p fs , ad9467 - 250 0 20 40 60 80 100 120 ?65 ?55 ?45 ?35 ?25 ?23 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 snr/sfdr (db) analog input leve l (dbfs) snr fs sfdr fs sfdr dbc snr dbc 09029-132 figure 32 . snr/sfdr vs. analog input level, f in = 97 .3 mhz, 2.5 v p - p fs, ad9467 -200 0 20 40 60 80 100 120 ?65 ?55 ?45 ?35 ?25 ?23 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 snr/sfdr (db) analog input leve l (dbfs) 09029-133 sfdr fs sfdr dbc snr fs snr dbc figure 33 . snr/sfdr vs. analog input level, f in = 97.3 mhz, 2.5 v p - p fs, ad9467 - 250
ad9467 data sheet rev. d | page 16 of 32 70 75 80 85 90 95 100 snr/sfdr (dbfs) tempera ture (c) ?40 ?30 ?20 ?10 0 20 10 30 40 50 60 70 80 ?35 ?25 ?15 ?5 5 25 15 35 45 55 65 75 85 sinad sfdr 09029-134 figure 34 . sinad/sfdr vs. temperature, f in = 97 .3 mhz, 2.5 v p - p fs, ad9467 - 200 70 75 80 85 90 95 100 snr/sfdr (dbfs) tempera ture (c) ?40 ?30 ?20 ?10 0 20 10 30 40 50 60 70 80 ?35 ?25 ?15 ?5 5 25 15 35 45 55 65 75 85 sinad sfdr 09029-135 figure 35 . sinad/sfdr vs. temperature, f in = 97 .3 mhz, 2.5 v p - p fs, ad9467 - 250 6000 12000 18000 24000 36000 42000 60000 30000 48000 54000 3.75 09029-136 inl error (lsb) code 3.00 2.25 1.50 0.75 0 0.75 ?1.50 ?2.25 ?3.00 ?3.75 figure 36 . inl, f in = 4.3 mhz, 2.5 v p - p fs, ad9467 - 200 6000 12000 18000 24000 36000 42000 60000 30000 48000 54000 09029-137 dnl error (lsb) code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 figure 37 . dnl, f in = 4.3 mhz, 2.5 v p - p fs, ad9467 - 200 10000 20000 30000 40000 50000 60000 6 8 09029-138 inl error (lsb) code 4 2 0 ?2 ?4 ?6 ?8 figure 38 . inl, f in = 4.3 mhz, 2.5 v p - p fs, ad9467 - 250 6000 12000 18000 24000 36000 42000 60000 30000 48000 54000 09029-139 dnl error (lsb) code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 figure 39 . dnl, f in = 4.3 mhz, 2.5 v p - p fs, ad9467 - 250
data sheet ad9467 rev. d | page 17 of 32 20 30 40 50 60 70 80 90 100 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 snr/sfdr (dbfs/dbc) analog input common-mode vo lt age (v) de f au l t cmv sfdr snr 09029-140 figure 40 . snr/sfdr vs. analog input common - mode voltage, ain = 100 mhz, 2.5 v p - p fs, ad9467 - 250 20 30 40 50 60 70 80 90 100 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 snr/sfdr (dbfs/dbc) analog input common-mode vo lt age (v) de f au l t cmv sfdr snr 09029-141 figure 41 . snr/sfdr vs. analog input common - mode voltage, ain = 100 mhz, 2.5 v p - p fs, ad9467 - 200 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 50 100 150 200 250 300 cmrr (db) frequenc y (mhz) 09029-142 figure 42 . c ommon - mode rejection ratio (cmrr), ad9467 - 250 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 amplitude (db) frequenc y (hz) 1m 10m 100m 1g 10g ? 3db = 2.24ghz 09029-143 figure 43 . c onverter ac bandwidth ad9467 - 250 140,000 120,000 100,000 80,000 60,000 40,000 20,000 0 n ? 17 n ? 16 n ? 15 n ? 14 n ? 13 n ? 12 n ? 11 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 code number of hits 09029-144 3.427lsb rms figure 44 . input - referred noise hi stogram, 2.5 v p - p fs, ad9467 - 20 0 140,000 120,000 100,000 80,000 60,000 40,000 20,000 0 n ? 17 n ? 16 n ? 15 n ? 14 n ? 13 n ? 12 n ? 11 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 code number of hits 09029-145 3.385lsb rms figure 45 . input - referred noise hi stogram, 2.5 v p - p fs, ad9467 - 25 0
ad9467 data sheet rev. d | page 18 of 32 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 70 80 90 100 1 10 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 psrr (db) analog input frequenc y (mhz) a vdd1 a vdd2 dr vdd 09029-146 figure 46 . power supply rejection (psr), ad9467 - 250 70 75 80 85 90 95 100 0 50 100 150 200 250 300 sfdr (dbfs) buffer current percen t age (%) 4mhz 97mhz 140mhz 170mhz 210mhz 290mhz 09029-247 figure 47 . sfdr performance vs. buffer current percentage over analog input frequency, ad9467 - 20 0 75 80 85 90 95 100 105 0 50 100 150 200 250 300 sfdr (dbfs) buffer current percen t age (%) 4mhz 97mhz 140mhz 170mhz 210mhz 290mhz 09029-248 figure 48 . sfdr performance vs. buffer current percentage over analog input frequency , ad9467 - 250
data sheet ad9467 rev. d | page 19 of 32 theory of operation the ad9467 architecture consists of an input - buffered pipe - lined adc that consists of a 3 - bit first stage, a 4 - bit second stage, followed by four 3 - bit stages and a final 3- bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stage. the input buffer provides a linear high input impedance (for ease of drive) and reduces the kick - back from the adc . the buffer is optimized for high l inearity, low noise , and low power. the quantized outputs from each stage are combined into a final 16- bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample while the remain ing st ages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for exam ple, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate di gital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. analog input conside rations the analog input to the ad9467 is a differen tial buffer. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common - mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the ana log inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single - ended signal. in either case, a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and , therefore , achieve the maxi mum bandwidth of the adc. such u se of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the in put to limit unwanted broadband noise. see the an - 742 application note , the an - 827 application note , the an - 935 application note, and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the appl i cation. for best dynamic performance, the source impedances driving vin+ and vin ? should be matched such that common - mode settling errors are symmetrical. these errors are reduced by the common - mode rejection of the adc. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the default case of the ad9467 , the largest input span available is 2 .5 v p - p. for other input full - scale options , see the full - scale and reference options section. sfdr optimization buffer current adjustment using re gister 36 and register 107, the buffer currents can be changed as a percentage to optimize the sfdr over various input frequencies and bandwidths of interest. as the input buffer currents are set , this does change the amount of current required by avdd2 . h owever, the current consumption is small in comparison to the overall currents required by this supply. the current specifications listed in table 1 incorporate this variation. for a complete list of buffer current settings , see table 13 for more details. the following buffer current settings reflect the performance that can be achieved using the input networks as described in figure 51 and figure 52 . these curves describe the percentages used to obtain data sheet typical specification s for both the 250 msps and 200 msps parts. for example, when using ifs from 150 mhz to 250 mhz, 160% is actual ly the average of the entire buffer current. therefore, both register 36 and register 107 need to be set to 160%. ad9467bcpz - 250 b uffer c urrent settings: ? dc to 150 mhz at 80% ( d efault s etting) ? 150 mhz to 250 mhz at 160% ? 250 m hz and higher at 210% 80 82 84 86 88 90 92 94 96 98 100 0 50 100 150 200 250 300 sfdr (dbfs) analog input frequenc y (mhz) 80% 160% 210% 09029-147 figure 49 . buffer current sweeps, 2.5 v p- p, ad9467 - 250
ad9467 data sheet rev. d | page 20 of 32 ad9467bcpz - 200 b uffer c urrent settings: ? dc to 150 mhz at 80% ( d efault s etting) ? 150 mhz to 250 mhz at 100% ? 250 mhz and higher at 160% 80 82 84 86 88 90 92 94 96 98 100 sfdr (dbfs) analog input frequenc y (mhz) 80% 100% 160% 09029-148 0 50 100 150 200 250 300 figure 50 . buffer current sweeps, 2. 5 v p- p, ad9467 - 20 0 note that for sample rates less than 150 msps and analog inputs less than 100 mhz, it is recommende d to set the buffer current to 0%. depending on the input network design and frequency band of interest, the optimum b uffer current settings may be slightly different than the input network recommendations shown in figure 53 and figure 54. differential input configurations there are several ways to drive the ad9467 , either actively or passively ; however, optimum performance is achieved by driving the analog input differentially. for applications where snr and sfdr are key p arameter s, differential transfor mer coupling is the recommended inpu t configuration (see figure 51 and figure 52 ) because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9467 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed ( see figure 51, figure 52 , and figure 53 ) using the adl5562 or adl5201 differential driver s to drive the ad9467 pr o vides an excellent and flexible gain option to interface to the adc (see figure 54 and figure 56 ) for both baseband and high if applications. using an amplifier also pr ovide s better isolation from the preceding stages as well as better pass - band flatness. p erformance plot s of these amplifiers can also be seen in figure 55 and figure 57. w hen using any dc - coupled amplifier , the user has the option to disconnect the input common - mode voltage buffer from the analog inputs. this allows the common - mode output pin of the amplifier to set this voltage between the interface of the two devices . oth er - wise, use an ac coupling capacitor in series on each of the analog input as shown in figure 54 for if applica tions that do no t require dc coupling. see the memory map se ction for more details. ain+ ain? 3.5pf ? adc internal input z ad9467 4.7pf ? ? 0.1f 0.1f 0.1f 0.1f ? ? sma ? ? adt1-1wt 0.1f 0.1f adt1-1wt 10nh 0.1f input = ? 09029-040 3.3v 1.8v 16 notes 1. all connections and power supply decoupling not shown. figure 51 . differential transformer - coupled configuration for baseband applications up to 150 mhz ain+ ain? 3.5pf ? adc internal input z ad9467 1.8pf ? ? 0.1f 0.1f 0.1f 0.1f ? ? sma ? ? adt1-1wt 0.1f 0.1f adt1-1wt 10nh 0.1f input = ? 09029-041 3.3v 1.8v 16 notes 1. all connections and power supply decoupling not shown. figure 52 . differential transformer - coupled configuration for if applications f rom 150 mhz to 300 mhz 1 2 3 4 5 6 7 8 anaren bd0205f5050a00 c3 ) c2 ) c1 ) analog in r2 r1 r8 r7 r6 r5 r3 r4 c6 8.2pf c5 8.2pf ain? ain+ ad9467 09029-151 3.3v 1.8v 16 notes 1. al l connections and power supp ly decoupling not shown. figure 53 . wideband balun - coupled configuration for if applications up greater than 1 00 mhz
data sheet ad9467 rev. d | page 21 of 32 5pf 750? ad9467 0.1f 3.3v 1:1 ratio ac 0.1f 0.1f 0.1f 20? 20? 15? 220nh 220nh 40? 50? 40? 15? 09029-254 adl5562 3.3v 1.8v 16 notes 1. all connections and power supply decoupling not shown. figure 54 . wideband differential amplifier input c onfiguration using the adl5562 0 15 30 45 75 90 4 6 3 5 2 * 120 60 105 0 09029-255 amplitude (db) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ain = ?1dbfs snr = 73.8dbfs sfdr = 91.1dbfs if = 100mhz f s = 250msps figure 55 . single - tone fft performance plot u sing the adl5562 a mplifier , gain = 6 db , and the ad9467 - 25 0 09029-256 14pf 75? 75? digital interface ad9467 0.1f 0.1f 0.1f 1h 0.1f 5v 1:3 ratio ac 0.1f 33? 33? 47nh 47nh 50? 5v 1h 5v ad5201 3.3v 1.8v 16 notes 1. all connections and power supply decoupling not shown. figure 56 . wideband differential vga input configuratio n using the adl5201 0 15 30 45 75 90 4 6 3 5 2 * 120 60 105 0 09029-257 amplitude (db) frequency (mhz) ?15 ?30 ?45 ?60 ?75 ?90 ?105 ?120 ?135 ain = ?1dbfs snr = 69.2dbfs sfdr = 88.8dbfs if = 100mhz f s = 250msps figure 57 . single - tone fft performance plot u sing the adl5201 vga , gain = 20 db , and the ad9467 - 250
ad9467 data sheet rev. d | page 22 of 32 clock input consider ations for optimum performance, the ad9467 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this s ignal is typically ac - coupled to the clk+ and clk? pins via a transformer or capacitors. these pins are biased i n ternally and require no add i tional bias ing . figure 58 shows a preferred method for clocking the ad9467 . the low jitter clock source is converted from a single- ended signal to a differential signal using an rf transformer. the back - to - back schottky diodes across the secondary transformer limit clock excursion s into the ad9467 to approximately 0.8 v p - p diffe r ential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9467 , and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottk y diodes: hsm2812 50? 100? clk? clk+ adc xfmr 09029-056 mini-circuits ? adt1-1w t , 1:1 z clock input figure 58 . transformer - coupled differential clock a nother option is to ac - couple a differential pecl or lvds signal to the sample clock input pins , as shown in fig ure 59 and figure 60 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 / ad9520 / ad9522 / ad9523 / ad9524 family of clock drivers o f fers excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50 ? 1 50 ? 1 clk clk 1 50 ? resis t ors are optional. clk? clk+ adc 09029-057 pecl driver clock input clock input figure 59 . differential pecl sample clock 10 0? 0.1f 0.1f 0.1f 0.1f 50? 1 l vds driver 50? 1 clk clk 1 50? resis t ors are optional. clk? clk+ adc 09029-058 clock input clock input figure 60 . differential lvds sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sens i tive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9467 contains a duty cycle stab i lizer (dcs) that retimes the nonsampling edge, pr oviding an internal clock signal with a nom i nal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the perfor m ance of the ad9467 . a ny changes to the sampling fr e quency require several clock cycles to allow the internal ti ming to acquire and lock at the new sampling rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input fr e quency (f a ) due only to aperture jitter ( t j ) can be calc u lated by snr = 20 log 10(2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if unde r sampling appli cations are particularly sensitive to jitter (see figure 61). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9467 . power supplies for clo ck drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of source (by ga ting, dividing, or other met h ods), it should be retimed by the original clock at the last step. refer to the an- 501 application note and the an - 756 application note for more in - depth information about jitter performance as it relates to adcs. 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps anal og i npu t f requ ency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 09029-061 figure 61 . ideal snr vs. input frequency and jitter
data sheet ad9467 rev. d | page 23 of 32 power dissipation and power - down mode as shown in figure 62 , the power dissipated by the ad9467 is proportional to its sample rate. the output power dissipation does not vary much b e cause it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 100 1 10 120 130 140 150 160 170 180 190 200 210 220 power (w) current (ma) sample r a te (msps) i a vdd1 i dr vdd i a vdd2 total power 09029-157 figure 62 . supply current vs. f sample for f in = 5 mhz, ad9467 - 20 0 1.08 1.10 1.12 1.14 1.16 1.18 1.20 0 0.1 0.2 0.3 0.4 0.5 0.6 210 215 220 225 230 235 240 245 250 power (w) current (ma) sample r a te (msps) 09029-158 i a vdd1 i dr vdd i a vdd2 total power figure 63 . supply current vs. f sample for f in = 5 mhz, ad9467 - 250 by asserting the power -d own option via the spi register map (0x08[1:0]) , the ad9467 is placed in to power - down mode. in this state, the adc typically dissipates 5 m w. d u r i n g p o w e r - down, the lvds output drivers are placed in a high impedance state. in power - down mode, low power dissipation is achieved by shutting down the internal reference, reference bu ff er, digital output, and biasing networks. the device require s approx - imately 100 ms to restore full operation. see the memory map section for more details on using these features. power supplies to achieve the best dynamic performance of the ad9467 , it is recommended that each power supply pin be decoupled as closely to the package as possible with 0.1 f, x7r or x5r type decoupling capacitors. for optimum performance, all supplies should be at typical values or slightly higher to accommodate elevated temperature drifts , which depend on the application. full - scale and reference options the analog in puts support both an input full scale of 2.5 v p- p (default) and 2.0 v p- p differentially. choosing one full - sc ale input range over the other present s some trade - offs t o the user. using an input full scale of 2.5 v p- p yields the best snr performance. if system trade - offs require improved sfdr performance , then a 2.0 v p- p input full scale should be used. however, in this mode, snr degrade s by roughly 2 db. other input full - scale ranges are available for use between 2.0 v p -p and 2.5 v p-p. see register 18 in table 13 and the memory m ap section for details. the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve gain matching when using multiple adcs. the internal reference can be dis abled via the spi, allowing the use of an external reference. see the memory map section for more details. the external reference is loaded by the input of an internal buffer amplifier having 3 pf of capacitance to ground. th ere is also a 1 k? internal resistor in series with the input of that buffer. the external reference must be limited to a nominal 1.25 v for an input full - scale swing of 2.5 v p- p. additional capacitance may be necessary to keep this pin quiet depending on the external reference used. when not using the xvref pin , it must be tied to ground directly or through a 0.1 f decoupling capacitor . however, keep this pin quiet regardless. digital outputs and timing the ad9467 differential outputs conform to the ansi - 644 lvds standard on default power - up. the lvds driver current is derived on chip and sets t he output current at each output equal to a nominal 3.0 ma. a 100 ? differential termination resistor placed at the lvds receive r inputs results in a nominal 30 0 mv swing at the receiver. the ad9467 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in no isy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as clos e to the receiver as possible. if there is n o far - end receiver termination or there is poor differential trace routing , timing errors may result . to avoid such timing errors, i t is recommended that the trace length be no longer than 18 inches and that the differential output traces be kept close together and at eq ual lengths. an example of the dco and data with proper trace length and posit ion is shown in figure 64 .
ad9467 data sheet rev. d | page 24 of 32 ch1 500mv ? ch2 500mv ? ch3 500mv ? 5.0ns/div 20.0gs/s it 25.0pt/pt a ch2 10.0v 1 2 3 clock dco data 09029-159 figure 64 . output timing example in lvds mode (default), ad9467 - 250 an example of the lvds output using the ansi - 644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of six inches on standard fr -4 material is shown in figure 65 . it is the responsibility of the user to determine if the waveforms meet the timing budget of the design . 400 0 ?2 ?1 0 1 2 ?20 ?10 0 10 voltage (mv) time (ns) 300 200 100 ?100 ?200 ?300 ?400 14 0 2 4 6 8 10 12 tie jitter histogram (hits) time (ps) 20 30 40 09029-160 figure 65 . data eye for lvds outputs in ansi - 644 mode with 6 - inch trace lengths on standard fr - 4, ad9467 -2 50 ?40 ?20 0 40 60 50 tie jitter histogram (hits) time (ps) 45 40 35 30 25 20 15 10 5 0 20 09029-161 400 0 ?2 ?1 0 1 2 voltage (mv) time (ns) 300 200 100 ?100 ?200 ?300 ?400 figure 66 . data eye for lvds outputs in ansi - 644 mode with 18 - inch trace lengths on standard fr - 4, ad9467 - 250 the format of the output data is offset binary by default. an example of the output coding format can be found in table 8 . t o change the output data format to twos complement or gra y code , see the memory map section. table 8 . digital output coding code vin vin input span 2 .5 v p p v d igital output offset binary d15 : d0 65, 536 +1.25 1111 1111 1111 1111 32, 768 0.00 1000 0000 0000 0000 32, 767 ?0.00003 8 0111 1111 1111 1111 0 ?1.25 0000 0000 0000 0000 an output clock is provided to assist in cap turing data from the ad9467 . data is clocked out of the ad9467 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. see the timing diagram shown in figure 2 for more information.
data sheet ad9467 rev. d | page 25 of 32 there are eight digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to tab le 10 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns may not adhere to the data format select option . the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a descrip - tion of the pn sequence and how it is generated can be found in s ection 5.1 of the itu - t 0.150 (05/96) standard. t he only difference is that the starting value must be a specific value instead of all 1s (s ee table 9 for the initial values ). the pn s equence l ong pattern produces a pseudorandom bit sequence that repeats itself every 2 23 C 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s (see table 9 for the initial values) and the ad9467 inverts the bit stream with r elation to the itu standard. table 9 . pn sequence sequence initial value first three output samples (msb first) pn 9 sequence, short 0xffff 0x87be, 0xae64, 0x929d pn 23 sequence , long 0x7 fff 0x7e00, 0x807c, 0x801f consult the memory map section for information on how to change these additional digital output timing features through the spi. over r ange (or) output pins the or+ and or ? output pins indicate when an applied analog input is above or below the input full scale of the converter. if the analog input is in an over range condition, the or bit go es high , coinciding with output data hit ting above or below full - scale. the delay be tween the time the part actually over ranges and the or bit going high is the pipeline latency of the part. spi pins: sclk, sdio, csb for normal spi operation, these pins should be tied to agnd through a 100 k? resistor on each pin. these pins are both 1.8 v and 3.3 v tolerant. however, the sdio output logic level is dependent on the bias of the spi vdd pin . for 3.3 v output logic, tie spi vdd to 3.3 v (avdd2). for 1.8 v output logic, tie spi vdd to 1.8 v (avdd1). the csb pin should be tied to avdd1 for applic ations that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. table 10 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a 1 n/a 1 n/a 1 0001 midscale short 1000 0000 0000 0000 same yes 0010 +full - scale short 1111 1111 1111 11 11 same yes 0011 ?full - scale short 0000 0000 0000 0000 same yes 0100 checkerboard 1010 1010 1010 1010 0101 0101 0101 0101 no 0101 pn sequence long 2 n/a 1 n/a 1 yes 0110 pn sequenc e short 2 n/a 1 n/a 1 yes 0111 one - /zero - word toggle 1111 1111 1111 1111 0000 0000 0000 0000 no 1 n/a = not applicable. 2 all test mode options except pn sequence short and pn sequence long can support 8 - to 14 - bit word lengths to verify data capture to the receiver.
ad9467 data sheet rev. d | page 26 of 32 serial port interface (spi) the ad9467 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. this gives the user added flexibility and customization , depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided down into fields, as detailed in the memory map section. detailed operational information can be found in the an - 877 application note, interfacing to high speed adcs via spi . there are three pins that define the spi : sclk, sdio, and csb (see table 11) . the sclk pin is used to synchronize the read and write data presented to the adc. the sdio pin is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active low control that enables or disables the read and write cycles. table 11 . serial port pins pin function sclk serial c lock. the serial shift clock in put . sclk is used to synchronize serial interface reads and writes. sdio serial d ata i nput/ o utput. a dual - purpose pin. the typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. csb chip s elect b ar ( a ctive l ow). this control gates the read and write cycles. the falling edge of the csb , in conjunction with the rising edge of the sclk , determines the start of the framing sequence. during an instruction phase, a 16 - bit instruction is transmitted followed by one or more data bytes, w hich is determined b y bit field w0 and bit field w1. an example of the serial timing and its definitions can be found in figure 68 and table 12 . during normal operation, csb is used to sign al to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to process instructions. normally, csb remains low until the communication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streami ng mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory transfers without requiring additional instructions. regardless of the mode, if csb is taken high in the m iddle of a byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port configuration influences how the ad9467 operate s . when operating in 2 - wire mode, it is recommended to use a 1 - , 2 - , or 3- byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change from an input to an output at the appropriate point in the serial frame. data can b e sent in msb - or lsb - first mode. msb - first mode is the default at power - up and can be changed by adjusting the configuration register. for more information about this and other features, see the an- 877 applica tion note , interfacing to high speed adcs via spi . hardware interface the pins described in table 11 compose the physical interface between the programming device of the user and the serial port of the ad9467 . t he sclk and csb pins function as inputs when using the spi. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdio pins share a common connection, care should be taken to ensure that p roper v oh levels are met. assuming the same load for each ad9467 , figure 67 shows the number of sdio pins that can be connected together and the resulting v oh level. 1.80 1.79 1.78 1.77 1.76 1.75 1.74 1.73 1.72 0 10 20 30 40 50 60 70 80 90 100 number of sdio pins connected together v oh (v) 09029-074 figure 67 . sdio pin loading this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers , providing the user with an alternative method, other than a full spi controller, to program the adc (see the an - 812 application note ).
data sheet ad9467 rev. d | page 27 of 32 don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t high t clk t low t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 09029-072 figure 68 . serial timing details table 12 . serial timing definitions parameter timing ( minimum , ns) description t ds 5 set up time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t high 16 minimum period that sclk should be in a logic high state t lo w 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 68 ) t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 68 )
ad9467 data sheet rev. d | page 28 of 32 memory map reading the memory m ap table each row in the memory map register table ( see table 13) has eight address locations. the memory map is divided into three sections: the chip configuration register map (address 0x00 to address 0x02), the device index and transfer register map (address 0xff), and the ad c functions register map (address 0x08 to address 0x 107 ). the left most column of the memory map indicates the register address number , and t he default value is shown in the second right - most column. the (msb) bit 7 column is the start of the default hexa decimal value given. for example, address 0x2c , the analog input register , h as a default value of 0x00 , mean ing bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 0, or 0000 0000 in binary. this setting is the default for an ac - coupled analog input condition. by writing a 1 to bit 2 of this address, the internal input common - mode b uffer is disabled allowing a dc - coupled input for which the input common mode voltage can be set externally . for more information on this an d other functions, consult the an - 877 application note, interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values sug gested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power - up. default values when the ad9467 c om es out of a reset, critical registers are preloaded with default va lues. these values are indicated in table 13 , where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writi ng logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. table 13 . memory map register 1 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 (lsb) bit 0 default value (hex) default notes/ comments chip configuration register 00 chip_port_config x lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 x x x 0x18 the nibbles should be mirrored so that lsb - or msb- first m ode is set correctly regard less of shift mode. 01 chip_id 8- bit chip id bits [ 7:0 ] (ad9467 = 0x50 , default) read only default is unique chip id, different for each device. this is a read - only register. 02 chip_grade x child id bits [ 6:4 ] (identify device variants of c hip id) 00 1 = 200 msps 010 = 250 msps x x x x read only child id used to differentiate graded devices. device index and transfer regi ster ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers dat a from the master shift register to the slave.
data sheet ad9467 rev. d | page 29 of 32 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 (lsb) bit 0 default value (hex) default notes/ comments adc functions 08 modes x x x x x x internal power - down mode 00 = chip run (default) 01 = full power - down 0x00 determines various generic modes of chip operation. 0d test_io x x reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test mode see table 10 in the digital outputs and timing section 0000 = off (default) 0001 = midscale shor t 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one - /zero - word toggle 0x00 when this register is set, the test data is placed on the output pins in place of normal data. 0f adc_input xvref 1 = on 0 = off (default) x x x x analog disconnect 1 = on 0 = off (default) x x 0x0 0 analog i nput f unctions . 10 offset 8- bit digital offset adjustment 0111 1111 = 127 0111 1110 = 126 0000 0010 = 2 0000 000 1 = 1 0000 0000 = 0 1111 1111 = -1 1 111 1110 = -2 1000 0001 = - 126 1000 0000 = - 127 0x00 bipolar , twos complement d igital o ffset adjustment in lsbs. 14 output_mode x 0 x digital o utput d is able 1 = on 0 = off (default) 1 output invert 1 = on 0 = off (default) data f ormat s elect 00 = offset binary (d efault) 01 = twos complement 10 = gray c ode 0x08 configures the outputs and the format of the data. 15 output_adjust x x x x coarse lvds a djust 0 = 3.0 ma (default) 1 = 1.71 ma output c urrent d rive a djust 001 = 3.0 ma (default) 010 = 2.79 ma 011 = 2.57 ma 100 = 2.35 ma 101 = 2.14 ma 110 = 1.93 ma 111 = 1.71 ma 0x00 determines lvds or other output properties. 16 output_phase dco o utput invert 1 = on 0 = off (default) x x x x x x x 0x00 determines digital clock output phase . 18 vref x x x x input f ull -sc ale r ange a djust 0000 = 2.0 v p-p 0110 = 2.1 v p-p 0111 = 2.2 v p-p 1000 = 2.3 v p-p 1001 = 2.4 v p-p 1010 = 2.5 v p- p (default) 0x0a
ad9467 data sheet rev. d | page 30 of 32 addr. (hex) parameter name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 (lsb) bit 0 default value (hex) default notes/ comments 2c analog_input x x x x x input c oupling m ode 0 = ac c oupling (default) 1 = dc c oupling x x 0x00 determines the input co upling mode . 36 buffer current select 1 110101 = +530% 110100 = +520% 001000 = +80% (default) 000010 = +20% 000001 = +10% 000000 = n ominal , 0% 111111 = ? 10% 111110 = ? 20% 110111 = ? 90% 110110 = ? 100% 1 0 0x2 2 107 buffer current select 2 110101 = +530% 110100 = +520% 001000 = +80% (default) 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = ?10% 111110 = ?20% 110111 = ?90% 110110 = ?100% x x 0x20 1 x = undefined feature, dont write .
data sheet ad9467 rev. d | page 31 of 32 power and ground recommendations when connecting power to the ad9467, it is recommended that three separate supplies be used: one for analog avdd1 and avdd3 (1.8 v), one for analog avdd2 (3.3 v), and one for dig ital output drivers drvdd (1.8 v). if only one 1.8 v supply is available, it should be routed to avdd1 a nd av dd3 f irst and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user can empl oy several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts, with minimal trace lengths. a single pc board ground plane should be suffic ient when using the ad9467 . with proper decoupling and smart parti - tioning of the pc boards analog, digital, and clock sections, optimum performance can be easily achieved. exposed paddle thermal heat slug recommendations it is required that the e xposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9467 . an exposed continuous copper plane on the pcb should be con - nected to the ad9467 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be so lder- filled or plugged. to maximize the coverage and adhesion between the adc an d pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process , whereas using one continuous plane with no partitions only guarantees one tie point. see figure 69 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 app lication note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . silkscreen p artition pin 1 indic at or 09029-073 figure 69 . typical pcb layout
ad9467 data sheet rev. d | page 32 of 32 outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indic at or sea ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic at or coplanarit y 0.08 06-25-2012-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed p ad bot t om view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 8.60 8.50 sq 8.40 figure 70 . 72 - lead lead frame chip scale package, expo s ed pad [lfcsp _vq ] 10 mm 10 mm body, very thin quad (cp - 72 -5) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9467bcpz -200 C 40c to +85c 72- lead lfcsp_vq cp -72 -5 ad9467bcpzrl7 - 200 C 40c to +85c 72 - lead lfcsp_vq cp - 72 - 5 ad9467 bcp z- 250 C 40c to +85c 72- lead lfcsp _vq cp -72 -5 ad9467bcpzrl7 - 250 C 40c to +85c 72- lead lfcsp_vq cp -72 -5 ad9467 - 200ebz ad9467 - 200 evaluation board ad9467 - 250ebz ad9467 - 250 evaluation board ad9467 - fmc - 250ebz ad9467 - 250 native fmc card 1 z = rohs compliant part. ? 2010 C 2013 a nalog devices, inc. all rights reserved. trademarks and reg istered trademarks are the property of their respective owners. d09029 -0- 2/1 3 (d )

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